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CHAPTER 2 V
R
4120A
Preliminary User’s Manual S15543EJ1V0UM
159
Figure 2-61. Common Exception Handling (1/2)
(a) Handling Exceptions other than Cold Reset, Soft Reset, NMI, and TLB/XTLB Refill (Hardware)
BD bit
1
EPC
PC
4
EXL
1
Kernel mode is set and interrupts
are disabled.
= 0 (Normal) = 1 (bootstrap)
Check for multiple exceptions
Kernel mode is set and interrupts are
disabled.
EntryHi and X/Context registers are set only
when a TLB Refill, TLB Invalid, or TLB
Modified exception occurs.
X/Context
VPN2
Entry Hi
VPN2, ASID
Set Cause register (ExcCode, CE)
)
To guideline to common exception handler
Start
Yes
EXL = 1?
(SR1)
No
NoYes
Instruction
in branch delay
slot?
BEV
PC
FFFF FFFF BFC0 0200H +180H
(Unmapped, uncached space)
M16 = 1?
(config20)
PC
FFFF FFFF 8000 0000H +180H
(Unmapped, cacheable space)
No
Instruction
in delay slot?
BD bit
1
EPC
PC
4
EPC
EIM
BD bit
0
EPC
PC
EPC
EIM
NoYes
Yes
BD bit
0
EPC
PC
BadVAddr is set only when a TLB Refill, TLB
Invalid, or TLB Modified exception occurs
(BadVAddr is not set when a Bus Error exception
occurs).
Remark The interrupts can be masked by setting the IE or IM bit.
The Watch exception can be set to pending state by setting the EXL bit to 1.
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