Nec switch Uživatelský manuál

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Strany 1 - PD789800 Subseries

User’s ManualµµµµPD789800µµµµPD78F9801µµµµPD789800 Subseries8-Bit Single-Chip MicrocontrollersPrinted in JapanDocument No. U12978EJ3V0UD00 (3rd edit

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User’s Manual U12978EJ3V0UD10TABLE OF CONTENTSCHAPTER 1 GENERAL...

Strany 3 - NOTES FOR CMOS DEVICES

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD100Figure 8-3. Block Diagram of USB TimerInternal busUWDERRINTUSBTMfXUSBCLKRESUME RXNoteClear

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD101(1) Receive bank switching ID detection buffer (internal buffer)This is an internal 2-bit bu

Strany 5 - Regional Information

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD102(3) Receive token bank(a) Receive token PID (USBRTP)This is the receive token packet ID area

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD103(4) Receive data bank(a) Receive data PID (USBRD)This is the receive data packet ID area. T

Strany 7 - INTRODUCTION

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD104(5) Transmit data banks 0 and 1(a) Transmit data PID banks 0 and 1 (USBTD0 and USBTD1)USBTD0

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD105Figure 8-7. Configuration of Transmit Data Bank 1 (Buffer 1)Data area (8 bytes)USBPOW addre

Strany 9 - Other Related Documents

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD106(6) Data/handshake packet receive byte number counter (DRXCON)This register sets the number

Strany 10 - User’s Manual U12978EJ3V0UD

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD107(9) Token address compare register (ADRCMP)This register sets the address specified from the

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD108(10) Data/handshake PID compare register (DIDCMP)This register sets the data/handshake packe

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1098.4 Registers Controlling USB FunctionThe following nine registers are used to control the U

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User’s Manual U12978EJ3V0UD113.3.4 Register addressing ...

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD110Figure 8-11. Format of Data/Handshake Packet Receive Mode RegisterSymbol 67 5 4 3 <2>

Strany 15 - LIST OF FIGURES (1/4)

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD111(3) Packet receive status register (RXSTAT)This register indicates the receive status of eac

Strany 16 - LIST OF FIGURES (2/4)

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD112Figure 8-12. Format of Packet Receive Status RegisterSymbol 67 543210UWDERRRESMRX SE0RX URE

Strany 17 - LIST OF FIGURES (3/4)

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD113Table 8-2 shows the state of each flag after receiving the USB reset signal and the Resume s

Strany 18 - LIST OF FIGURES (4/4)

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD114Figure 8-14. Format of Token Packet Receive Result Store RegisterSymbol <6><7>

Strany 19 - LIST OF TABLES (1/2)

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD115(6) Data packet transmit reservation register (DTXRSV)This register sets the bank where the

Strany 20 - LIST OF TABLES (2/2)

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD116(7) Handshake packet transmit reservation register (HTXRSV)This register sets the handshake

Strany 21 - 1.3 Ordering Information

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD117Figure 8-16. Format of Handshake Packet Transmit Reservation Register (2/2)ACKEN ACK packet

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD118Table 8-3. Conditions in Transmit Reservation (2/2)(b) Transmit reservation for Endpoint1 a

Strany 23 - 1.5 78K/0S Series Lineup

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD119Figure 8-17. Configuration of Handshake Packet Transmit Reservation RegisterEND1RXEND0RXTID

Strany 24 - MIN.Value

User’s Manual U12978EJ3V0UD12CHAPTER 7 WATCHDOG TIMER ...

Strany 25 - Series for ASSP

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD120(8) USB timer start reservation control register (USBTCL)This register reserves USB timer st

Strany 26 - 1.6 Block Diagram

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD121(9) Remote wake-up control register (REMWUP)This register transmits the Resume signal to per

Strany 27 - 1.7 Functions

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1228.5 USB Function Operation8.5.1 USB timer operationThe USB timer is a 7-bit counter that per

Strany 28 - 2.1 List of Pin Functions

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD123Figure 8-20. Flowchart of USB Timer Operation (1/2)SYNC detected?EOP received?SETORX(intern

Strany 29 - (2) Non-port pins

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD124Figure 8-20. Flowchart of USB Timer Operation (2/2)2INTUSBTM occurredHigh-speed mode overfl

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1258.5.2 Remote wakeup control operationFigure 8-21. Flow Chart of Remote Wakeup Control Opera

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD126Notes 1. Be sure to follow the exact instruction sequence when the Resume signal (“K” state)

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1278.6 Interrupt Request from USB Function8.6.1 Interrupt sourcesInterrupt request sources gene

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD128(3) Data/handshake packet transmit interrupt (INTUSBST)Upon EOP detection during data/handsh

Strany 34 - Figure 2-1. Pin I/O Circuits

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1298.6.2 Cautions when using interruptsPay attention to the following when using an interrupt r

Strany 35 - 3.1 Memory Space

User’s Manual U12978EJ3V0UD1311.4.2 Maskable interrupt acknowledgment operation...

Strany 36 - PD78F9801)

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1308.7 USB Function Control8.7.1 Relationship between packets and operation modesThe relationsh

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD131(2) Control transfer (OUT) (Transfer byte count: 9 bytes or more)RequestOperation of host co

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD132(3) Control transfer (IN) (Transfer byte count: 8 bytes or less)RequestOperation of hostcont

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD133(4) Control transfer (IN) (Transfer byte count: 9 bytes or more)RequestOperation of hostcont

Strany 40 - Z 0 AC 0 0 1 CY

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD134(5) No data controlRequestOperation of hostcontrollerIN packetSETUPDATA0ACKPacket fromhost c

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD135(6) Interrupt transferOperation of host controllerIN packetINNAK Packet fromhost controller

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1368.7.2 Interrupt servicing flow(1) USB token packet reception interrupt servicingINTUSBRT occ

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD137(2) Data/handshake packet reception interrupt servicingINTUSBRD occurrenceRETIPlanned packet

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD138(3) USB timer inadvertent program loop detection interrupt servicingINTUSBTM occurrenceRETIP

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD139(4) 1 ms timer interrupt servicing INTTM00 occurrenceRETIREMOTE WAKEUP?Standby detected?Comm

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User’s Manual U12978EJ3V0UD14B.1 Register Index (Alphabetic Order of Register Name) ...229B.2

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1408.8 USB Function Internal Circuit Operations8.8.1 Operation of transmit/receive pointerFigu

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD141Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (2/7)(1) Token packet receptio

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD142Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (3/7)(2) Data/Handshake packet

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD143Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (4/7)(2) Data/Handshake packet

Strany 51 - Identifier Description

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD144Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (5/7)(3) Data packet transmit

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD145Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (6/7)(3) Data packet transmit

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD146Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (7/7)(4) Handshake packet tran

Strany 54 - Register specification code

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1478.8.2 Receive bank switching ID detection buffer operationFigure 8-26. Flowchart of Receive

Strany 55 - Instruction code 00101011

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1488.8.3 Sync detection/USBCLK detector operationThis circuit generates the USBCLK signal (1.5

Strany 56 - — [HL+byte]

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD149Figure 8-29. Flowchart of Sync Detection/USBCLK Detector OperationNYNYNYYNIdle stateUSB clo

Strany 57 - 4.1 Port Functions

User’s Manual U12978EJ3V0UD15LIST OF FIGURES (1/4)Figure No. Title Page2-1 Pin I/O Circuits ...

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1508.8.4 NRZI encoder operationThis circuit performs NRZI encoding of data to be transmitted.Fi

Strany 59 - 4.2 Port Configuration

CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD1518.8.5 Bit stuffing/strip controller operationThis circuit counts the number of “logic 1” of

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD152Figure 8-33. Flow Chart of Bit Stuffing Control OperationYYYNNIdle stateIdle stateTransmit

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD153Figure 8-34. Flow Chart of Bit Strip Control OperationYYYNNIdle stateIdle stateReceive bit

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User’s Manual U12978EJ3V0UD154CHAPTER 9 SERIAL INTERFACE 109.1 Functions of Serial Interface 10Serial interface 10 has the following two modes.

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CHAPTER 9 SERIAL INTERFACE 10User’s Manual U12978EJ3V0UD1559.2 Configuration of Serial Interface 10Serial interface 10 consists of the followin

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CHAPTER 9 SERIAL INTERFACE 10User’s Manual U12978EJ3V0UD156Figure 9-1. Block Diagram of Serial Interface 10Internal busCSIE10 TPS100 DIR10Seri

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CHAPTER 9 SERIAL INTERFACE 10User’s Manual U12978EJ3V0UD1579.3 Register Controlling Serial Interface 10The following register is used to contro

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CHAPTER 9 SERIAL INTERFACE 10User’s Manual U12978EJ3V0UD158Table 9-2. Operating Mode Settings of Serial Interface 10(1) Operation stop modeCSI

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CHAPTER 9 SERIAL INTERFACE 10User’s Manual U12978EJ3V0UD1599.4 Operation of Serial Interface 10Serial interface 10 provides the following two m

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User’s Manual U12978EJ3V0UD16LIST OF FIGURES (2/4)Figure No. Title Page6-7 Interval Timer Operation Timing of 8-Bit Timer/Event Counter 01...

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CHAPTER 9 SERIAL INTERFACE 10User’s Manual U12978EJ3V0UD1609.4.2 3-wire serial I/O modeThe 3-wire serial I/O mode is useful for connection of p

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CHAPTER 9 SERIAL INTERFACE 10User’s Manual U12978EJ3V0UD161(2) Communication operationIn the 3-wire serial I/O mode, data transmission/receptio

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User’s Manual U12978EJ3V0UD162CHAPTER 10 REGULATORThe µPD789800 incorporates a regulator that powers the USB driver/receiver. The features are a

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User’s Manual U12978EJ3V0UD163CHAPTER 11 INTERRUPT FUNCTIONS11.1 Interrupt Function TypesThe following two types of interrupt functions are used

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD164Table 11-1. Interrupt Source ListType of Interrupt PriorityNote 1Interrupt SourceNa

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD165Figure 11-1. Basic Configuration of Interrupt Function(A) Internal non-maskable in

Strany 75 - 5.4 System Clock Oscillators

CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD16611.3 Registers Controlling Interrupt FunctionThe following five registers are used t

Strany 76 - (n = 0, 1, 2, 4)

CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD167(1) Interrupt request flag registers (IF0 and IF1)The interrupt request flag is set

Strany 77 - 5.5 Clock Generator Operation

CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD168(2) Interrupt mask flag registers (MK0 and MK1)The interrupt mask flag is used to en

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD169(4) Program status word (PSW)The program status word is a register used to hold the

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User’s Manual U12978EJ3V0UD17LIST OF FIGURES (3/4)Figure No. Title Page8-31 Flow Chart of NRZI Encoder Operation ...

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD170(5) Key return mode register 00 (KRM00)This register sets the pin that detects a key

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD17111.4 Interrupt Servicing Operation11.4.1 Non-maskable interrupt acknowledgment opera

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD172Figure 11-8. Flowchart of Non-Maskable Interrupt Request AcknowledgmentStartWDTM4 =

Strany 83 - TCL011TCL010

CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD17311.4.2 Maskable interrupt acknowledgment operationA maskable interrupt can be acknow

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD174Figure 11-12. Timing of Interrupt Request Acknowledgment (Example of MOV A,r)ClockC

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD17511.4.3 Multiplexed interrupt servicingServicing in which another interrupt is acknow

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD176Figure 11-14. Example of Multiplexed Interrupt ServicingExample 1. Acknowledging m

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CHAPTER 11 INTERRUPT FUNCTIONSUser’s Manual U12978EJ3V0UD17711.4.4 Interrupt request holdIf an interrupt (such as a maskable, non-maskable, or e

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User’s Manual U12978EJ3V0UD178CHAPTER 12 STANDBY FUNCTION12.1 Standby Function and Configuration12.1.1 Standby functionThe standby function is u

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CHAPTER 12 STANDBY FUNCTIONUser’s Manual U12978EJ3V0UD17912.1.2 Register controlling standby functionThe wait time after the STOP mode is releas

Strany 90 - 00H 01H 02H 03H 04H

User’s Manual U12978EJ3V0UD18LIST OF FIGURES (4/4)Figure No. Title Page14-3 Example of Connection with Dedicated Flash Programmer ...

Strany 91 - 7.1 Watchdog Timer Functions

CHAPTER 12 STANDBY FUNCTIONUser’s Manual U12978EJ3V0UD18012.2 Standby Function Operation12.2.1 HALT mode(1) HALT modeThe HALT mode is set by exe

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CHAPTER 12 STANDBY FUNCTIONUser’s Manual U12978EJ3V0UD181(2) Releasing HALT modeThe HALT mode can be released by the following three sources.(a)

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CHAPTER 12 STANDBY FUNCTIONUser’s Manual U12978EJ3V0UD182(c) Releasing by RESET inputWhen the HALT mode is released by the RESET signal, executi

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CHAPTER 12 STANDBY FUNCTIONUser’s Manual U12978EJ3V0UD18312.2.2 STOP mode(1) Setting and operation status of STOP modeThe STOP mode is set by ex

Strany 95 - 7.4 Watchdog Timer Operation

CHAPTER 12 STANDBY FUNCTIONUser’s Manual U12978EJ3V0UD184(2) Releasing STOP modeThe STOP mode can be released by the following two sources.(a) R

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CHAPTER 12 STANDBY FUNCTIONUser’s Manual U12978EJ3V0UD185(b) Releasing by RESET inputWhen the STOP mode is released by the RESET signal, the res

Strany 97 - 8.1 USB Overview

User’s Manual U12978EJ3V0UD186CHAPTER 13 RESET FUNCTIONThe following two operations are available to generate reset signals.(1) External reset

Strany 98 - 8.2 USB Function Features

CHAPTER 13 RESET FUNCTIONUser’s Manual U12978EJ3V0UD187Figure 13-2. Reset Timing by RESET InputX1RESETInternalreset signalPort pinDuring normal

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CHAPTER 13 RESET FUNCTIONUser’s Manual U12978EJ3V0UD188Table 13-1. Hardware Status After Reset (1/2)Hardware Status After ResetProgram counter

Strany 100 - CHAPTER 8 USB FUNCTION

CHAPTER 13 RESET FUNCTIONUser’s Manual U12978EJ3V0UD189Table 13-1. Hardware Status After Reset (2/2)Hardware Status After ResetUSB function Dat

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User’s Manual U12978EJ3V0UD19LIST OF TABLES (1/2)Table No. Title Page2-1 Type of Pin I/O Circuit Recommended Connection of Unused Pins ...

Strany 102 - USBPOW address

User’s Manual U12978EJ3V0UD190CHAPTER 14 µµµµPD78F9801The µPD78F9801 is a product that substitutes flash memory for the internal ROM of the mask

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD19114.1 Flash Memory CharacteristicsFlash memory programming is performed by connecting a ded

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD19214.1.2 Communication modeUse the communication mode shown in Table 14-2 to perform communi

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD193Figure 14-3. Example of Connection with Dedicated Flash Programmer(a) 3-wire serial I/ODe

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD194If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programm

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD19514.1.3 On-board pin processingWhen performing programming on the target system, provide a

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD196(1) Signal conflictIf the dedicated flash programmer (output) is connected to a serial inte

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD197<RESET pin>If the reset signal of the dedicated flash programmer is connected to the

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD19814.1.4 Connection of adapter for flash writingThe following figure shows an example of rec

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CHAPTER 14 µµµµPD78F9801User’s Manual U12978EJ3V0UD199Figure 14-9. Wiring Example for Flash Writing Adapter with Pseudo-3-Wire Method12 13 14

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User’s Manual U12978EJ3V0UD2[MEMO]

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User’s Manual U12978EJ3V0UD20LIST OF TABLES (2/2)Table No. Title Page12-3 STOP Mode Operation Status ...

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User’s Manual U12978EJ3V0UD200CHAPTER 15 INSTRUCTION SETThis chapter lists the instruction set of the µPD789800 Subseries. For details of the o

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD20115.1.2 Description of “operation” columnA: A register; 8-bit accumulatorX: X registerB:

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD20215.2 Operation ListMnemonic Operands Bytes Clocks Operation FlagZACCYMOV r,#byte 3 6 r ←

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD203Mnemonic Operands Bytes Clocks Operation FlagZACCYMOVW rp,#word 3 6 rp ← wordAX,saddrp 2

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD204Mnemonic Operands Bytes Clocks Operation FlagZACCYSUBC A,#byte 2 4 A,CY ← A−byte−CY ×××s

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD205Mnemonic Operands Bytes Clocks Operation FlagZACCYCMP A,#byte 2 4 A−byte ×××saddr,#byte

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD206Mnemonic Operands Bytes Clocks Operation FlagZACCYCALL !addr16 3 6 (SP−1) ← (PC+3)H, (SP

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD20715.3 Instructions Listed by Addressing Type(1) 8-bit instructionsMOV, XCH, ADD, ADDC, SU

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD208(2) 16-bit instructionsMOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW2nd Operand1st

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CHAPTER 15 INSTRUCTION SETUser’s Manual U12978EJ3V0UD209(4) Call instructions/branch instructionsCALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ2nd Oper

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User’s Manual U12978EJ3V0UD21CHAPTER 1 GENERAL1.1 Features• On-chip USB functions• Implements a USB (Universal Serial Bus) by connecting to Hub a

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User’s Manual U12978EJ3V0UD210CHAPTER 16 ELECTRICAL SPECIFICATIONSAbsolute Maximum Ratings (TA = 25°°°°C)Parameter Symbol Conditions Rating Unit

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD211System Clock Oscillation Circuit Characteristics (TA = −−−−40 to +85°°°°C, VD

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD212DC Characteristics (TA = −−−−40 to +85°°°°C, VDD = 4.0 to 5.5 V) (1/2)Paramete

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD213DC Characteristics (TA = −−−−40 to +85°°°°C, VDD = 4.0 to 5.5 V) (2/2)Paramet

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD214AC Characteristics(1) Basic operations (TA = −−−−40 to +85°°°°C, VDD = 4.0 to

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD215(b) 3-wire serial I/O mode (TA = −−−−40 to +85°°°°C, VDD = 4.0 to 5.5 V)(i)

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD216AC Timing Measurement Points (Except X1 Input and USB Function)0.8VDD0.2VDD0.8

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD217Serial Transfer TimingUSB function:USBDM and USBDP rise/fall timeUSBDM, USBDP

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CHAPTER 16 ELECTRICAL SPECIFICATIONSUser’s Manual U12978EJ3V0UD218Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA =

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User’s Manual U12978EJ3V0UD219CHAPTER 17 PACKAGE DRAWINGS33342244112112344 PIN PLASTIC LQFP (10x10)ITEM MILLIMETERSNQ0.1±0.050.10S44GB-80-8ES-2J

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CHAPTER 1 GENERALUser’s Manual U12978EJ3V0UD221.4 Pin Configuration (Top View)• 44-pin plastic LQFP (10 × 10)µPD789800GB-×××-8ES, µPD78F9801GB-8E

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User’s Manual U12978EJ3V0UD220CHAPTER 18 RECOMMENDED SOLDERING CONDITIONSThe µPD789800 Subseries should be soldered and mounted under the follo

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User’s Manual U12978EJ3V0UD221APPENDIX A DEVELOPMENT TOOLSThe following development tools are available for development of systems using the µPD

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APPENDIX A DEVELOPMENT TOOLSUser’s Manual U12978EJ3V0UD222Figure A-1. Development ToolsLanguage processing software· Assembler package· C compi

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APPENDIX A DEVELOPMENT TOOLSUser’s Manual U12978EJ3V0UD223A.1 Software PackageSoftware tools for development of the 78K/0S Series are combined

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APPENDIX A DEVELOPMENT TOOLSUser’s Manual U12978EJ3V0UD224Remark ×××× in the part number differs depending on the host machine and operating sys

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APPENDIX A DEVELOPMENT TOOLSUser’s Manual U12978EJ3V0UD225A.5 Debugging Tools (Hardware)IE-78K0S-NSIn-circuit emulatorIn-circuit emulator for d

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APPENDIX A DEVELOPMENT TOOLSUser’s Manual U12978EJ3V0UD226A.6 Debugging Tools (Software)This debugger supports the in-circuit emulators IE-78K0

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APPENDIX A DEVELOPMENT TOOLSUser’s Manual U12978EJ3V0UD227A.7 Notes on Target System DesignFigures A-2 and A-3 show the conditions when connect

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APPENDIX A DEVELOPMENT TOOLSUser’s Manual U12978EJ3V0UD228Figure A-3. Connection Condition of Target System (NP-H44GB-TQ)Emulation boardIE-7898

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User’s Manual U12978EJ3V0UD229APPENDIX B REGISTER INDEXB.1 Register Index (Alphabetic Order of Register Name)8-bit compare register 00 (CR00) ..

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CHAPTER 1 GENERALUser’s Manual U12978EJ3V0UD231.5 78K/0S Series LineupThe products in the 78K/0S Series are listed below. The names enclosed in

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APPENDIX B REGISTER INDEXUser’s Manual U12978EJ3V0UD230Port mode register 2 (PM2)...

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APPENDIX B REGISTER INDEXUser’s Manual U12978EJ3V0UD231B.2 Register Index (Alphabetic Order of Register Symbol)[A]ADRCMP: Token address compare

Strany 149 - Sync detection

APPENDIX B REGISTER INDEXUser’s Manual U12978EJ3V0UD232PU0: Pull-up resistor option register 0 ...

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User’s Manual U12978EJ3V0UD233APPENDIX C REVISION HISTORYThe revision history is described below. The “Applied to” column indicates the chapter

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APPENDIX C REVISION HISTORYUser’s Manual U12978EJ3V0UD234(2/2)Edition Major Revisions from Previous Edition Applied to:Correction of address val

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CHAPTER 1 GENERALUser’s Manual U12978EJ3V0UD24The major differences between subseries are shown below.Series for General-Purpose and LCD DriveTim

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CHAPTER 1 GENERALUser’s Manual U12978EJ3V0UD25Series for ASSPTimer VDDFunctionSubseriesROMCapacity(Bytes)8-Bit 16-Bit Watch WDT8-BitA/D10-BitA/DS

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CHAPTER 1 GENERALUser’s Manual U12978EJ3V0UD261.6 Block DiagramKey return 08-bit timer 008-bit timer/event counter 01Watchdog timerRegulatorUSBfu

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CHAPTER 1 GENERALUser’s Manual U12978EJ3V0UD271.7 FunctionsProductItemµPD789800µPD78F9801Internal memory ROM Mask ROM8 KBFlash memory16 KBHigh-sp

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User’s Manual U12978EJ3V0UD28CHAPTER 2 PIN FUNCTIONS2.1 List of Pin Functions(1) Port pinsPin Name I/O Function After Reset AlternateFunctionP00

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CHAPTER 2 PIN FUNCTIONSUser’s Manual U12978EJ3V0UD29(2) Non-port pinsPin Name I/O Function After Reset AlternateFunctionINTP0 Input External int

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User’s Manual U12978EJ3V0UD3NOTES FOR CMOS DEVICES1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORSNote:Strong electric field, when exposed to a MOS device

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CHAPTER 2 PIN FUNCTIONSUser’s Manual U12978EJ3V0UD302.2 Pin Functions2.2.1 P00 to P07 (Port 0)These pins constitute an 8-bit I/O port and can be

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CHAPTER 2 PIN FUNCTIONSUser’s Manual U12978EJ3V0UD312.2.4 P40 to P47 (Port 4)These pins constitute an 8-bit I/O port. In addition, they also fu

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CHAPTER 2 PIN FUNCTIONSUser’s Manual U12978EJ3V0UD322.2.12 VPP (µµµµPD78F9801 only)A high voltage should be applied to this pin when the flash m

Strany 162 - CHAPTER 10 REGULATOR

CHAPTER 2 PIN FUNCTIONSUser’s Manual U12978EJ3V0UD332.3 Pin I/O Circuits and Recommended Connection of Unused PinsTable 2-1 lists the types of I

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CHAPTER 2 PIN FUNCTIONSUser’s Manual U12978EJ3V0UD34Figure 2-1. Pin I/O CircuitsType 2Type 5-RType 8-FType 24-AType 8-CINSchmitt-triggered inpu

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User’s Manual U12978EJ3V0UD35CHAPTER 3 CPU ARCHITECTURE3.1 Memory SpaceThe µPD789800 Subseries can access 64 KB of memory space.Figures 3-1 and

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD36Figure 3-2. Memory Map (µµµµPD78F9801)ReservedFlash memory16,384 × 8 bitsInternal high-s

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD373.1.1 Internal program memory spaceThe internal program memory space stores programs and

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD383.1.4 Data memory addressingThe µPD789800 Subseries provides a variety of addressing mode

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD39Figure 3-4. Data Memory Addressing (µµµµPD78F9801)Special function registers (SFR)256 ×

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User’s Manual U12978EJ3V0UD4These commodities, technology or software, must be exported in accordance with the export administration regulations of t

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD403.2 Processor RegistersThe µPD789800 Subseries provides the following on-chip processor r

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD41(a) Interrupt enable flag (IE)This flag controls interrupt request acknowledgment operati

Strany 172 - WDT: Watchdog timer

CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD42(3) Stack pointer (SP)This is a 16-bit register that holds the start address of the memor

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD433.2.2 General-purpose registersThe general-purpose registers consist of eight 8-bit regis

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD443.2.3 Special function registers (SFRs)Unlike general-purpose registers, each special fun

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD45Table 3-2. Special Function Register List (1/3)Address Special Function Register (SFR) N

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD46Table 3-2. Special Function Register List (2/3)Address Special Function Register (SFR) N

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD47Table 3-2. Special Function Register List (3/3)Address Special Function Register (SFR) N

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD483.3 Instruction Address AddressingAn instruction address is determined by program counter

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD493.3.2 Immediate addressing[Function]Immediate data in the instruction word is transferred

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User’s Manual U12978EJ3V0UD5Regional Information• Device availability• Ordering information• Product release schedule• Availability of related te

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD503.3.3 Table indirect addressing[Function]Table contents (branch destination address) of t

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD513.4 Operand Address AddressingThe following methods are available to specify the register

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD523.4.2 Short direct addressing[Function]The memory to be manipulated in the fixed space is

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD533.4.3 Special function register (SFR) addressing[Function]The memory-mapped special funct

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD543.4.4 Register addressing[Function]In the register addressing mode, general-purpose regis

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD553.4.5 Register indirect addressing[Function]In the register indirect addressing mode, mem

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CHAPTER 3 CPU ARCHITECTUREUser’s Manual U12978EJ3V0UD563.4.6 Based addressing[Function]8-bit immediate data is added to the contents of the base

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User’s Manual U12978EJ3V0UD57CHAPTER 4 PORT FUNCTIONS4.1 Port FunctionsThe µPD789800 Subseries provides the ports shown in Figure 4-1, enabling

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD58Table 4-1. Functions of PortsPin Name I/O Function After Reset AlternateFunctionP00 toP07I

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD594.2 Port ConfigurationPorts consists the following hardware.Table 4-2. Configuration of Po

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User’s Manual U12978EJ3V0UD6Major Revisions in This EditionPage ContentsDeletion of CU-type and GB-3BS type packagesThroughoutDeletion of indication

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD604.2.1 Port 0This is an 8-bit I/O port with an output latch. Port 0 can be specified in the

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD614.2.2 Port 1This is an 8-bit I/O port with an output latch. Port 1 can be specified in the

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD624.2.3 Port 2This is a 7-bit I/O port with an output latch. Port 2 can be specified in the

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD63Figure 4-5. Block Diagram of P21PU0: Pull-up resistor option register 0PM: Port mode regis

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD64Figure 4-6. Block Diagram of P22PU0: Pull-up resistor option register 0PM: Port mode regis

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD65Figure 4-7. Block Diagram of P23 and P24Internal busWRPU0RDWRPORTWRPMPU02Output latch(P23,

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD66Figure 4-8. Block Diagram of P25RDVDD0P25WRPOM1WRPU0WRPORTWRPMOutput latch(P25)PM25PU02P-c

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD67Figure 4-9. Block Diagram of P26RDVDD0P26WRPOM1WRPU0WRPORTWRPMOutput latch(P26)PM26PU02P-c

Strany 200 - 15.1 Operation

CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD684.2.4 Port 4This is an 8-bit I/O port with an output latch. Port 4 can be specified in the

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD694.3 Registers Controlling Port FunctionThe following three types of registers control the p

Strany 202 - 15.2 Operation List

User’s Manual U12978EJ3V0UD7INTRODUCTIONReaders This manual is intended for users who wish to understand the functions of theµPD789800 Subseries and

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD70Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate FunctionsSeco

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD71(3) Port output mode registers (POM0 and POM1)The port output mode registers (POM0 and POM1

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CHAPTER 4 PORT FUNCTIONSUser’s Manual U12978EJ3V0UD724.4 Port Function OperationThe operation of a port differs depending on whether the port is

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User’s Manual U12978EJ3V0UD73CHAPTER 5 CLOCK GENERATOR5.1 Clock Generator FunctionsThe clock generator generates the clock to be supplied to the

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CHAPTER 5 CLOCK GENERATORUser’s Manual U12978EJ3V0UD745.3 Register Controlling Clock GeneratorThe clock generator is controlled by the following

Strany 208 - SET1, CLR1, NOT1, BT, BF

CHAPTER 5 CLOCK GENERATORUser’s Manual U12978EJ3V0UD755.4 System Clock Oscillators5.4.1 System clock oscillatorThe system clock oscillator is os

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CHAPTER 5 CLOCK GENERATORUser’s Manual U12978EJ3V0UD765.4.2 Examples of incorrect resonator connectionFigure 5-4 shows examples of incorrect res

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CHAPTER 5 CLOCK GENERATORUser’s Manual U12978EJ3V0UD77Figure 5-4. Examples of Incorrect Resonator Connection (2/2)(e) Signals are fetched VSS0

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CHAPTER 5 CLOCK GENERATORUser’s Manual U12978EJ3V0UD785.6 Changing Setting of CPU Clock5.6.1 Time required for switching CPU clockThe CPU clock

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User’s Manual U12978EJ3V0UD79CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 016.1 Functions of 8-Bit Timer/Event Counters 00 and 01The 8-bit ti

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User’s Manual U12978EJ3V0UD8Related Documents The related documents indicated in this publication may include preliminary versions.However, prelimina

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD80(3) Square wave outputA square wave of arbitrary frequency can be

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD81Figure 6-2. Block Diagram of 8-Bit Timer/Event Counter 01Interna

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD826.3 Registers Controlling 8-Bit Timer/Event Counters 00 and 01The

Strany 217 - USBDM, USBDP

CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD83(2) 8-bit timer mode control register 01 (TMC01)TMC01 determines

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD84(3) Port mode register 2 (PM2)This register sets port 2 input/out

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD856.4 Operation of 8-Bit Timer/Event Counters 00 and 016.4.1 Operat

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD86Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00Cle

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD876.4.2 Operation as external event counter (timer 01 only)The exte

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD886.4.3 Operation as square-wave output (timer 01 only)The 8-bit ti

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD89Figure 6-9. Timing of Square-Wave OutputClear ClearInterrupt ack

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User’s Manual U12978EJ3V0UD9Other Related DocumentsDocument Name Document No.SEMICONDUCTOR SELECTION GUIDE - Products and Packages - (CD-ROM) X13769

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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01User’s Manual U12978EJ3V0UD906.5 Notes on Using 8-Bit Timer/Event Counters 00 and 01(1) Error

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User’s Manual U12978EJ3V0UD91CHAPTER 7 WATCHDOG TIMER7.1 Watchdog Timer FunctionsThe watchdog timer has the following functions.• Watchdog time

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CHAPTER 7 WATCHDOG TIMERUser’s Manual U12978EJ3V0UD927.2 Watchdog Timer ConfigurationThe watchdog timer consists of the following hardware.Table

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CHAPTER 7 WATCHDOG TIMERUser’s Manual U12978EJ3V0UD937.3 Registers Controlling Watchdog TimerThe following two registers are used to control the

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CHAPTER 7 WATCHDOG TIMERUser’s Manual U12978EJ3V0UD94(2) Watchdog timer mode register (WDTM)This register sets the operation mode of the watchdo

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CHAPTER 7 WATCHDOG TIMERUser’s Manual U12978EJ3V0UD957.4 Watchdog Timer Operation7.4.1 Operation as watchdog timerThe watchdog timer detects an

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CHAPTER 7 WATCHDOG TIMERUser’s Manual U12978EJ3V0UD967.4.2 Operation as interval timerWhen bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer

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User’s Manual U12978EJ3V0UD97CHAPTER 8 USB FUNCTION8.1 USB OverviewThe USB (Universal Serial Bus) is suitable for connecting personal computers

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD988.2 USB Function FeaturesThe features of the on-chip USB function provided for the µPD789800

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CHAPTER 8 USB FUNCTIONUser’s Manual U12978EJ3V0UD99Figure 8-2. Block Diagram of USB FunctionInternal busInternal busUSBDPUSBDM• Handshake pack

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