NEC uPD75P3116 Uživatelský manuál

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1994
DATA SHEET
The
µ
PD75P3116 replaces the
µ
PD753108’s internal mask ROM with a one-time PROM, and features expanded
ROM capacity.
Because the
µ
PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the
development stage using the
µ
PD753104, 753106, or 753108, and for use in small-scale production.
Detailed information about functions is provided in the following User’s Manual. Be sure to read it before
designing:
µ
PD753108 User’s Manual: U10890E
FEATURES
Compatible with
µ
PD753108
Memory capacity:
• PROM: 16384 × 8 bits
• RAM: 512 × 4 bits
Can be operated in same power supply voltage range as the mask version
µ
PD753108
• VDD = 1.8 to 5.5 V
On-chip LCD controller/driver
QTOP
TM
microcontroller
Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.
This support includes writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part Number Package
µ
PD75P3116GC-AB8 64-pin plastic QFP (14 × 14)
µ
PD75P3116GK-8A8 64-pin plastic LQFP (12 × 12)
µ
PD75P3116GC-8BS 64-pin plastic LQFP (14 × 14)
Caution This device does not provide an internal pull-up resistor connection function by means of mask
option.
µ
PD75P3116
MOS INTEGRATED CIRCUIT
4-BIT SINGLE-CHIP MICROCONTROLLER
The mark shows major revised points.
Document No. U11369EJ3V0DS00 (3rd edition)
Date Published March 2002 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
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Strany 1 - PD75P3116

1994DATA SHEETThe µPD75P3116 replaces the µPD753108’s internal mask ROM with a one-time PROM, and features expandedROM capacity.Because the µPD75P311

Strany 2

µPD75P311610Data Sheet U11369EJ3V0DS3.2 Non-Port Pins (2/2)Pin Name I/O Alternate Function Status I/O CircuitFunction After Reset TypeS0 to S15Output

Strany 3

µPD75P311611Data Sheet U11369EJ3V0DS3.3 Pin I/O CircuitsThe I/O circuits for the µPD75P3116’s pins are shown in abbreviated form below.INVDDP-chN-chV

Strany 4

µPD75P311612Data Sheet U11369EJ3V0DS(Continued)Type F-B Type HType M-CType G-AType G-BType M-EOutputdisableVDDP-chN-chIN/OUTDataVDDP-chP.U.R.enableP.

Strany 5

µPD75P311613Data Sheet U11369EJ3V0DS3.4 Recommended Connection of Unused PinsTable 3-1. List of Unused Pin ConnectionsPin Recommended ConnectionP00/

Strany 6

µPD75P311614Data Sheet U11369EJ3V0DS4. Mk I AND Mk II MODE SELECTION FUNCTIONSetting the stack bank selection (SBS) register for the µPD75P3116 enabl

Strany 7

µPD75P311615Data Sheet U11369EJ3V0DS4.2 Setting of Stack Bank Selection (SBS) RegisterUse the stack bank selection register to switch between the Mk

Strany 8

µPD75P311616Data Sheet U11369EJ3V0DS5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, 753108The µPD75P3116 replaces the internal mask ROM in t

Strany 9

µPD75P311617Data Sheet U11369EJ3V0DS6. MEMORY CONFIGURATIONFigure 6-1. Program Memory MapNote Can only be used in the Mk II mode.Remark For instruct

Strany 10

µPD75P311618Data Sheet U11369EJ3V0DSFigure 6-2. Data Memory MapNote Memory bank 0 or 1 can be selected as the stack area.(32 × 4)256 × 4(224 × 4)128

Strany 11

µPD75P311619Data Sheet U11369EJ3V0DS7. INSTRUCTION SET(1) Representation and coding formats for operandsIn the instruction’s operand area, use the fo

Strany 12

µPD75P31162Data Sheet U11369EJ3V0DSFUNCTION OUTLINEItem FunctionInstruction execution time • 0.95, 1.91, 3.81, or 15.3 µs (main system clock: @ 4.19

Strany 13

µPD75P311620Data Sheet U11369EJ3V0DS(2) Operation conventionsA: A register; 4-bit accumulatorB: B registerC: C registerD: D registerE: E registerH: H

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µPD75P311621Data Sheet U11369EJ3V0DS(3) Description of symbols used in addressing areaRemarks 1. MB indicates access-enabled memory banks.2. In area

Strany 15

µPD75P311622Data Sheet U11369EJ3V0DSInstruction Mnemonic OperandNo. of MachineOperationAddressingSkipGroupBytes Cycle AreaConditionTransfer MOV A, #n

Strany 16

µPD75P311623Data Sheet U11369EJ3V0DSInstruction Mnemonic OperandNo. of MachineOperationAddressingSkipGroupBytes Cycle AreaConditionBit transfer MOV1

Strany 17

µPD75P311624Data Sheet U11369EJ3V0DSInstruction Mnemonic OperandNo. of MachineOperationAddressingSkipGroupBytes Cycle AreaConditionComparison SKE reg

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µPD75P311625Data Sheet U11369EJ3V0DSInstruction Mnemonic OperandNo. of MachineOperationAddressingSkipGroupBytes Cycle AreaConditionBranch BRNote 1add

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µPD75P311626Data Sheet U11369EJ3V0DSInstruction Mnemonic OperandNo. of MachineOperationAddressingSkipGroupBytes Cycle AreaConditionSubroutine CALLANo

Strany 20

µPD75P311627Data Sheet U11369EJ3V0DSInstruction Mnemonic OperandNo. of MachineOperationAddressingSkipGroupBytes Cycle AreaConditionSubroutine PUSH rp

Strany 21

µPD75P311628Data Sheet U11369EJ3V0DS8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFYThe program memory contained in the µPD75P3116 is a 16384 × 8-b

Strany 22

µPD75P311629Data Sheet U11369EJ3V0DS8.2 Program Memory Write ProcedureProgram memory can be written at high speed using the following procedure.(1) P

Strany 23

µPD75P31163Data Sheet U11369EJ3V0DSCONTENTS1. PIN CONFIGURATION (TOP VIEW)...

Strany 24

µPD75P311630Data Sheet U11369EJ3V0DSVPPVDDVDD + 1VDDVPPVDDX1Data output Data outputMD0/P30MD2/P32MD3/P33MD1/P31“L”D0/P60 to D3/P63D4/P50 to D7/P538.3

Strany 25

µPD75P311631Data Sheet U11369EJ3V0DS8.4 One-Time PROM ScreeningDue to its structure, the one-time PROM cannot be fully tested before shipment by NEC.

Strany 26

µµµµµPD75P311632Data Sheet U11369EJ3V0DS9. ELECTRICAL SPECIFICATIONSAbsolute Maximum Ratings (TA = 25˚C)Parameter Symbol Test Conditions Rating UnitP

Strany 27

µµµµµPD75P311633Data Sheet U11369EJ3V0DSMain System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)Resonator Recommended Con

Strany 28

µPD75P311634Data Sheet U11369EJ3V0DSSubsystem Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)Resonator Recommended Constant

Strany 29

µµµµµPD75P311635Data Sheet U11369EJ3V0DSDC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)Parameter Symbol Test Conditions MIN. TYP. MAX. Uni

Strany 30

µµµµµPD75P311636Data Sheet U11369EJ3V0DSDC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)Parameter Symbol Test Conditions MIN. TYP. MAX. Uni

Strany 31 - 125˚C 24 hours

µPD75P311637Data Sheet U11369EJ3V0DSAC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)Parameter Symbol Test Conditions MIN. TYP. MAX. UnitCPU

Strany 32

µµµµµPD75P311638Data Sheet U11369EJ3V0DSSerial Transfer Operation2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (TA = –40 to +85˚C,

Strany 33

µµµµµPD75P311639Data Sheet U11369EJ3V0DSSBI mode (SCK...Internal clock output (master)): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)Parameter Symbol Test

Strany 34

µPD75P31164Data Sheet U11369EJ3V0DS1. PIN CONFIGURATION (TOP VIEW)• 64-pin plastic QFP (14 × 14):µPD75P3116GC-AB8• 64-pin plastic LQFP (12 × 12):µPD7

Strany 35

µPD75P311640Data Sheet U11369EJ3V0DSAC Timing Test Points (Excluding X1, XT1 Input)Clock TimingTI0, TI1, TI2 TimingTI0, TI1, TI21/fTItTILtTIHX1 input

Strany 36

µPD75P311641Data Sheet U11369EJ3V0DSSerial Transfer Timing3-wire serial I/O mode2-wire serial I/O modetKCY1, 2tKL1, 2 tKH1, 2SCKSISOtSIK1, 2 tKSI1, 2

Strany 37

µPD75P311642Data Sheet U11369EJ3V0DStKCY3, 4tKH3, 4tKSI3, 4tSIK3, 4tKSO3, 4SCKSB0, 1tKL3, 4tSBKtKSBtKCY3, 4tKH3, 4tKSI3, 4tSIK3, 4tKSO3, 4SCKSB0, 1tK

Strany 38

µPD75P311643Data Sheet U11369EJ3V0DSData Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85˚C)Parameter Symbol Test

Strany 39

µPD75P311644Data Sheet U11369EJ3V0DSData Retention Timing (STOP Mode Release by RESET)Data Retention Timing (Standby Release Signal: STOP Mode Releas

Strany 40

µµµµµPD75P311645Data Sheet U11369EJ3V0DSDC Programming Characteristics (TA = 25 ±5˚C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V)Parameter Symbo

Strany 41

µPD75P311646Data Sheet U11369EJ3V0DSProgram Memory Write TimingProgram Memory Read TimingtVPStVDStXHtXLtItDStDHtDVtDFtDStDHtAHtAStPWtM1RtM0StOPWtM1St

Strany 42

µµµµµPD75P311647Data Sheet U11369EJ3V0DS10. CHARACTERISTIC CURVES (REFERENCE VALUES)105.01.00.50.10.050.010.0050.001012345678(TA = 25°C)Supply voltag

Strany 43

µµµµµPD75P311648Data Sheet U11369EJ3V0DS105.01.00.50.10.050.010.0050.001012345678XT1 XT2X1 X2Crystal resonator4.19 MHzCrystal resonator32.768 kHz330

Strany 44

µPD75P311649Data Sheet U11369EJ3V0DS48493264117163364-PIN PLASTIC QFP (14x14)NOTEEach lead centerline is located within 0.15 mm ofits true position (

Strany 45

µPD75P31165Data Sheet U11369EJ3V0DSPIN IDENTIFICATIONSP00 to P03: Port 0 COM0 to COM3: Common output 0 to 3P10 to P13: Port 1 VLC0 to VLC2: LCD power

Strany 46

µPD75P311650Data Sheet U11369EJ3V0DS64-PIN PLASTIC LQFP (12x12)NOTEEach lead centerline is located within 0.13 mm ofits true position (T.P.) at maxim

Strany 47

µPD75P311651Data Sheet U11369EJ3V0DS64-PIN PLASTIC LQFP (14x14)NOTEEach lead centerline is located within 0.20 mm ofits true position (T.P.) at maxim

Strany 48 - Supply current IDD (mA)

µPD75P311652Data Sheet U11369EJ3V0DS12. RECOMMENDED SOLDERING CONDITIONSThe µPD75P3116 should be soldered and mounted under the conditions recommende

Strany 49

µPD75P311653Data Sheet U11369EJ3V0DSTable 12-1. Surface Mounting Type Soldering Conditions (2/2)(3)µPD75P3116GC-8BS: 64-pin plastic LQFP (14 × 14)Sol

Strany 50

µPD75P311654Data Sheet U11369EJ3V0DSAPPENDIX A. LIST OF µPD75308B, 753108, AND 75P3116 FUNCTIONSParameterµPD75308BµPD753108µPD75P3116Program memory

Strany 51

µPD75P311655Data Sheet U11369EJ3V0DSParameterµPD75308BµPD753108µPD75P3116Clock output (PCL) Φ, 524, 262, 65.5 kHz • Φ, 524, 262, 65.5 kHz(Main system

Strany 52

µPD75P311656Data Sheet U11369EJ3V0DSAPPENDIX B. DEVELOPMENT TOOLSThe following development tools have been provided for system development using the

Strany 53

µPD75P311657Data Sheet U11369EJ3V0DSPROM Write ToolsHardware PG-1500 This is a PROM writer that can program a single-chip microcontroller with PROM i

Strany 54

µPD75P311658Data Sheet U11369EJ3V0DSDebugging ToolsAn in-circuit emulator (IE-75001-R) is provided as a program debugging tool for the µPD75P3116.The

Strany 55

µPD75P311659Data Sheet U11369EJ3V0DSOS for IBM PCsThe following operating systems for IBM PCs are supported.OS VersionPC DOSTMVer.3.1 to 6.3J6.1/VNot

Strany 56

µPD75P31166Data Sheet U11369EJ3V0DS2. BLOCK DIAGRAMP20 to P23P00 to P03S0 to S151644444444COM0 to COM34BIASfLCDVPPVDDRESETVssCPU clock ΦStandbycontro

Strany 57

µPD75P311660Data Sheet U11369EJ3V0DSPackage Drawing and Recommended Footprint of Conversion Socket (EV-9200GC-64)Figure B-1. EV-9200GC-64 Package Dr

Strany 58

µPD75P311661Data Sheet U11369EJ3V0DSFigure B-2. EV-9200GC-64 Recommended Footprint (For Reference Only)FEDGHIJKLCBA0.031 × 0.591=0.4720.031

Strany 59

µPD75P311662Data Sheet U11369EJ3V0DSPackage Drawing of Conversion Adapter (TGK-064SBW)Figure B-3. TGK-064SBW Package Drawing (For Reference Only)ITE

Strany 60

µPD75P311663Data Sheet U11369EJ3V0DSNotes on Target System DesignThe following shows a diagram of the connection conditions between the emulation pro

Strany 61

µPD75P311664Data Sheet U11369EJ3V0DSFigure B-6. Connection Conditions of Target System (1)Figure B-7. Connection Conditions of Target System (2)In-

Strany 62

µPD75P311665Data Sheet U11369EJ3V0DSAPPENDIX C. RELATED DOCUMENTSThe related documents indicated in this publication may include preliminary version

Strany 63

µPD75P311666Data Sheet U11369EJ3V0DSOther Related DocumentsDocument Name Document No.SEMICONDUCTOR SELECTION GUIDE – Products & Packages – X1376

Strany 64

µPD75P311667Data Sheet U11369EJ3V0DS[MEMO]

Strany 65

µPD75P311668Data Sheet U11369EJ3V0DSNOTES FOR CMOS DEVICES1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORSNote:Strong electric field, when exposed to a MO

Strany 66

µPD75P311669Data Sheet U11369EJ3V0DSRegional InformationSome information contained in this document may vary from country to country. Before using a

Strany 67

µPD75P31167Data Sheet U11369EJ3V0DS3. PIN FUNCTIONS3.1 Port Pins (1/2)Pin Name I/O Alternate Function 8-Bit Status I/O CircuitFunction I/O After Rese

Strany 68

µPD75P3116QTOP is a trademark of NEC Corporation.MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States

Strany 69 - Regional Information

µPD75P31168Data Sheet U11369EJ3V0DS3.1 Port Pins (2/2)Pin Name I/O Alternate Function 8-Bit Status I/O CircuitFunction I/O After Reset TypeNote 1P60

Strany 70

µPD75P31169Data Sheet U11369EJ3V0DS3.2 Non-Port Pins (1/2)Pin Name I/O Alternate Function Status I/O CircuitFunction After Reset TypeNote 1TI0 Input

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